Semiconductor device and method of manufacturing the same

ABSTRACT

A semiconductor device according to the present invention includes a semiconductor layer provided with a gate trench, a first conductivity type source region formed to be exposed on a surface side of the semiconductor layer, a second conductivity type channel region formed on a side of the source region closer to a back surface of the semiconductor layer to be in contact with the source region, a first conductivity type drain region formed on a side of the channel region closer to the back surface of the semiconductor layer to be in contact with the channel region, a gate insulating film formed on an inner surface of the gate trench, and a gate electrode embedded inside the gate insulating film in the gate trench, while the channel region includes a channel portion formed along the side surface of the gate trench so that a channel is formed in operation and a projection projecting from an end portion of the channel portion closer to the back surface of the semiconductor layer toward the back surface.

CROSS-REFERENCE TO RELATED APPLICATION

This is continuation of U.S. application Ser. No. 15/336,985, filed on Oct. 28, 2016, and allowed on Oct. 30, 2017, which is a continuation of U.S. application Ser. No. 14/800,992, filed on Jul. 16, 2015, and issued on Nov. 22, 2016, as U.S. Pat. No. 9,502,495, which is, in turn, a continuation of U.S. application Ser. No. 14/147,614, filed on Jan. 6, 2014, and issued on Aug. 25, 2015, as U.S. Pat. No. 9,117,683, which was a division of U.S. application Ser. No. 13/590,665, filed on Aug. 21, 2012, and issued on Feb. 18, 2014, as U.S. Pat. No. 8,653,593. These prior US applications and the present continuation application claim the benefit of priority of Japanese applications 2011-183041, filed on Aug. 24, 2011, 2011-211443, filed on Sep. 27, 2011, and 2012-132261, filed on Jun. 11, 2012. The disclosures of these prior US and foreign applications are incorporated herein by reference.

BACKGROUND OF THE INVENTION Field of the Invention

The present invention relates to a semiconductor device including a trench gate MOSFET and a method of manufacturing the same.

Description of Related Art

As an example of a trench gate MOSFET, a semiconductor device according to Patent Document 1 (Japanese Unexamined Patent Publication No. 2010-62477), for example, includes an n⁻-type first base layer provided with a gate trench, a gate insulating film formed on the inner surface of the gate trench, a gate electrode charged into the gate insulating film, an interlayer dielectric film formed to cover the gate electrode, a p-type second base layer formed on the surface of the n⁻-type first base layer to be shallower than the bottom surface of the gate trench, an n⁺-type source layer formed on the surface of the p-type second base layer, a self-aligned contact trench formed into the p-type second base layer through the n⁺-type source layer, a source electrode connected to the p-type second base layer on the bottom surface of the self-aligned contact trench and connected to the n⁺-type source layer on the side surface of the self-aligned contact trench, an n⁺-type drain layer formed on the back surface of the n⁻-type first base layer, and a drain electrode formed on the n⁺-type drain layer.

SUMMARY OF THE INVENTION

A semiconductor device according to the present invention includes a semiconductor layer provided with a gate trench, a first conductivity type source region formed to be exposed on a surface side of the semiconductor layer for forming part of a side surface of the gate trench, a second conductivity type channel region formed on a side of the source region closer to a back surface of the semiconductor layer to be in contact with the source region for forming part of the side surface of the gate trench, a first conductivity type drain region formed on a side of the channel region closer to the back surface of the semiconductor layer to be in contact with the channel region for forming a bottom surface of the gate trench, a gate insulating film formed on an inner surface of the gate trench, and a gate electrode embedded inside the gate insulating film in the gate trench, while the channel region includes a channel portion formed along the side surface of the gate trench so that a channel is formed in operation and a projection projecting from an end portion of the channel portion closer to the back surface of the semiconductor layer toward the back surface.

According to the structure, part of the channel region projects toward the back surface of the semiconductor layer as the projection on a position different from the portion (the channel portion) where the channel is formed in operation. Thus, the area of a p-n junction interface can be increased without influencing channel characteristics of the semiconductor device as compared with a conventional structure having a constant depth from a surface of a semiconductor layer up to an interface (a p-n junction interface) between a channel region and a drain region. Therefore, the area of a depletion layer spreading from the p-n junction is also increased, whereby the depletion layer receives voltage with a large area. Consequently, the voltage received per unit area of the depletion layer can be reduced.

Also in a case where the quantity of projection of the gate trench toward the back surface of the semiconductor layer is small (the gate trench is shallow) with respect to the interface between the channel region and the drain region and withstand voltage cannot be ensured with only a depletion layer spreading from a small-area interface between the gate insulating film and the drain region, therefore, the large-area depletion layer is present in the vicinity of the projection of the channel region, whereby the withstand voltage of the overall semiconductor device can be improved.

Therefore, gate-to-drain capacitance can be reduced by shallowing the gate trench and reducing opposed areas of the gate electrode and the drain region while sufficiently holding source-to-drain withstand voltage.

Preferably, the semiconductor device further includes a contact trench passing through the source region from the surface of the semiconductor layer so that the deepest portion reaches the channel region and a second conductivity type channel contact region formed on a bottom surface of the contact trench, and the projection is formed immediately under the channel contact region.

The semiconductor device having such a structure can be manufactured by a method of manufacturing a semiconductor device according to the present invention including the steps of forming, in a semiconductor layer having a first conductivity type source region formed to be exposed on a surface side, a second conductivity type channel region formed on a side of the source region closer to a back surface to be in contact with the source region, and a first conductivity type drain region formed on a side of the channel region closer to the back surface to be in contact with the channel region, a gate trench passing through the source region and the channel region so that the deepest portion reaches the drain region, forming a gate insulating film on an inner surface of the gate trench, forming a gate electrode by embedding an electrode material inside the gate insulating film, forming a contact trench passing through the source region so that the deepest portion reaches the channel region in the semiconductor layer, forming a projection projecting from an end portion, closer to a back surface of the semiconductor layer, of a channel portion of the channel region formed along a side surface of the gate trench toward the back surface immediately under the contact trench by implanting second conductivity type ions to reach the vicinity of an interface between the channel region and the drain region through a bottom surface of the contact trench, and forming a channel contact region on the channel region by implanting second conductivity type ions into the vicinity of the bottom surface of the contact trench of the semiconductor layer.

According to the method, the projection can be easily formed on the channel region by introducing the second conductivity type ions into the bottom surface of the contact trench lower by one stage than the surface of the semiconductor layer through conventional ion implantation. The second conductivity type ions may be diffused into the semiconductor layer by performing annealing after the implantation of the second conductivity type ions, in response to the type of the material for the semiconductor layer. Such diffusion can be similarly performed also when forming the channel contact region.

The projection as formed projects in a direction separating from the channel contact region toward the back surface of the semiconductor layer, whereby a depletion layer spreading from the interface between the projection and the drain region can be prevented from coming into contact with the channel contact region. Therefore, reduction of the withstand voltage resulting from contact between the depletion layer and the channel contact region can be avoided.

In this case, a top portion of the projection immediately under the channel contact region may be formed along a position under a central portion in the width direction of the bottom surface of the contact trench.

The semiconductor device having such a structure can be manufactured by carrying out a step of perpendicularly implanting the second conductivity type ions into the bottom surface of the contact trench in the method of manufacturing a semiconductor device according to the present invention, for example.

According to the method, no precise angle adjustment is required in the implantation of the second conductivity type ions while the implantation angle may not be switched but the second conductivity type ions may simply be regularly perpendicularly implanted, whereby the projection can be more easily formed.

On the other hand, a top portion of the projection immediately under the channel contact region may be formed along a position under an end portion in the width direction of the bottom surface of the contact trench.

The semiconductor device having such a structure can be manufactured by carrying out a step of obliquely implanting the second conductivity type ions at an implantation angle inclining with respect to the bottom surface of the contact trench in the method of manufacturing a semiconductor device according to the present invention, for example.

When the top portion of the projection is formed along the position under the end portion in the width direction of the bottom surface of the contact trench, the top portion preferably includes a plurality of top portions formed in parallel with one another along positions under both end portions in the width direction of the bottom surface in particular. In other words, the projection preferably so projects as to have not a single top portion (peak) but a plurality of top portions (peaks).

The semiconductor device having such a structure can be manufactured by carrying out a first step of implanting the second conductivity type ions into an end portion in the width direction of the bottom surface of the contact trench and a second step of implanting the second conductivity type ions into another end portion in the width direction of the bottom surface of the contact trench in a direction intersecting with the direction of introduction of the second conductivity type ions in the first step when obliquely implanting the second conductivity type ions.

According to the method, the implantation angle of the second conductivity type ions must be switched when shifting from the first step to the second step, while the area of the interface between the projection and the drain region can be further increased due to the plurality of top portions (peaks) of the projection. Consequently, the voltage received per unit area of the depletion layer can be further reduced.

Preferably in the semiconductor device according to the present invention, a top portion of the projection is positioned on a side of the bottom surface of the gate trench closer to the back surface of the semiconductor layer, and the impurity concentration in the projection is not more than 1/100 of the concentration in the channel contact region. When the impurity concentration in the projection satisfies the aforementioned condition, the withstand voltage can be further improved.

The semiconductor layer may consist of an Si semiconductor layer.

In the method of manufacturing a semiconductor device according to the present invention, the step of forming the projection may include a single-stage implantation step of implanting the second conductivity type ions into a position of a prescribed depth from the bottom surface of the contact trench, or may include a multistage implantation step of implanting the second conductivity type ions into a prescribed depth from the bottom surface of the contact trench over a plurality of stages by varying implantation energy.

In the single-stage implantation step, the second conductivity type ions may be introduced into a depth position either on a side of the interface between the channel region and the drain region closer to the surface of the semiconductor layer or a side closer to the back surface.

In the multistage implantation step, the second conductivity type ions may be so implanted that a region defined by a plurality of stages of implanted portions extends over the sides of the interface between the channel region and the drain region closer to the surface and the back surface of the semiconductor layer so that some of implantation depths of the second conductivity type ions are on the surface side of the semiconductor layer and the rests are on the back surface side. Alternatively, the second conductivity type ions may be implanted so that the implantation depth of all second conductivity type ions is on the side of the interface between the channel region and the drain region closer to the surface or the back surface of the semiconductor layer.

Thus, a projection having any shape can be formed by selecting the single-stage or multistage ion implantation system and the implantation depth of the ions. Therefore, a projection having a proper shape can be formed in response to the shape and the depth of the gate trench and the shapes and the sizes of the impurity regions such as the source region and the channel region.

The foregoing and other objects, features and effects of the present invention will become more apparent from the following detailed description of the embodiments with reference to the attached drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic plan view of a trench gate MOS transistor according to an embodiment of the present invention.

FIG. 2 is a bird's-eye sectional view of the trench gate MOS transistor taken along a cutting plane line II-II in FIG. 1.

FIGS. 3A to 3J partially illustrate manufacturing steps for the trench gate MOS transistor shown in FIG. 2 in step order.

FIGS. 4A to 4D show modifications of an ion implantation system shown in FIG. 3G, and FIG. 4A shows an example of single-state implantation while FIGS. 4B to 4D show examples of multistage implantation respectively.

FIG. 5 is a graph showing the relation between dosages of B₁₁ ions and breakdown voltage.

FIG. 6 illustrates a modification of a projection of the trench gate MOS transistor shown in FIG. 1.

FIG. 7 is a diagram for illustrating ion implantation for forming the projection shown in FIG. 6.

FIG. 8 illustrates a first modification of a layout of unit cells of the trench gate MOS transistor shown in FIG. 1.

FIG. 9 illustrates a second modification of the layout of the unit cells of the trench gate MOS transistor shown in FIG. 1.

FIG. 10 is a schematic plan view of a MOS transistor according to an embodiment of Reference Example.

FIG. 11 is a bird's-eye sectional view of the MOS transistor taken along a cutting plane line XI-XI in FIG. 10.

FIGS. 12A to 12H partially illustrate manufacturing steps for the MOS transistor shown in FIG. 11 in step order.

FIGS. 13A and 13B show ON- and OFF-states of the MOS transistor shown in FIG. 11 respectively.

FIG. 14 illustrates a first modification of a layout of unit cells of the MOS transistor shown in FIG. 10.

FIG. 15 illustrates a second modification of the layout of the unit cells of the MOS transistor shown in FIG. 10.

DETAILED DESCRIPTION OF THE EMBODIMENTS

An embodiment of the present invention is now described in detail with reference to the attached drawings.

FIG. 1 is a schematic plan view of a trench gate MOS transistor according to the embodiment of the present invention. FIG. 2 is a bird's-eye sectional view of the trench gate MOS transistor taken along a cutting plane line II-II in FIG. 1.

Referring to FIG. 1, a MOS transistor 1 as a semiconductor device is a trench gate MOSFET (Metal Oxide Semiconductor Field-Effect Transistor), and includes a plurality of striped unit cells 2 arrayed in parallel with one another. The MOS transistor 1 is partitioned into the unit cells 2 by striped gate trenches 3, and the interval between each adjacent pair of gate trenches 3 (the pitch P of the gate trenches 3) is 0.9 μm to 1.5 μm, for example. Each unit cell 2 is provided with an elongated contact trench 4 (rectangular in plan view) extending from a first longitudinal end toward a second longitudinal end thereof.

Referring to FIG. 2, the MOS transistor 1 includes an Si substrate 5 of an n⁺ type (having a concentration of 1×10¹⁹ to 5×10¹⁹ cm⁻³, for example). The Si substrate 5 functions as a drain of the MOS transistor 1, and contains phosphorus (P), arsenic (As) or the like as an n-type impurity. This also applies to the following description.

An Si epitaxial layer 8 of an n⁻ type (having a concentration of 1×10¹⁶ to 1×10¹⁵ cm⁻³, for example) lower in concentration than the Si substrate 5 is stacked on a surface 6 (the upper surface) of the Si substrate 5. The thickness of the Si epitaxial layer 8 as a semiconductor layer is 3 μm to 10 μm, for example.

The gate trenches 3, having side surfaces 11 and bottom surfaces 12, dug down from a surface 9 of the Si epitaxial layer 8 toward the Si substrate 5 are formed in the Si epitaxial layer 8 in a striped manner. Thus, the plurality of striped unit cells 2 partitioned by the side surfaces 11 of the striped gate trenches 3 are formed in the Si epitaxial layer 8.

The depth D₁ of the gate trenches 3 measured from the surface 9 of the Si epitaxial layer 8 is 1.0 μm to 1.5 μm, for example, and more specifically, 1.0 μm.

In the Si epitaxial layer 8, source regions 13 of an n⁺ type and channel regions 14 of a p⁻ type (having a concentration of 1×10¹⁷ to 5×10¹⁷ cm⁻³, for example) are formed around the gate trenches 3 in this order from the side closer to the surface 9 of the Si epitaxial layer 8. The channel regions 14 contain boron (B), aluminum (Al) or the like, for example, as a p-type impurity. This also applies to the following description.

Each source region 13 is formed on a surface layer portion of each unit cell 2, to be exposed on the surface 9 of the Si epitaxial layer 8 and to form upper portions (part) of the side surfaces 11 of the corresponding gate trench 3. The thickness T₁ of the source region 13 along a direction from the surface 9 toward the Si substrate 5 is 0.2 μm to 0.4 μm, for example. In the following description, thicknesses are defined as those along the direction from the surface 9 toward the Si substrate 5, unless otherwise stated.

Each channel region 14 is formed on a side of the source region 13 closer to the Si substrate 5 (closer to a back surface 10 of the Si epitaxial layer 8) to be in contact with the source region 13 and to form lower portions (part) of the side surfaces 11 of the gate trench 3.

On the other hand, a region of the Si epitaxial layer 8 on a side of the channel region 14 closer to the Si substrate 5 is an n⁻-type drain region 15 maintaining a state after epitaxial growth as such. The drain region 15 is in contact with the channel region 14 on the side of the channel region 14 closer to the Si substrate 5, to form the bottom surface 12 of the gate trench 3.

A gate insulating film 16 is formed on the inner surfaces of the gate trench 3, to cover the whole area thereof. A gate electrode 17 is embedded in the gate trench 3 by charging polysilicon doped with an n-type impurity in a high concentration inside the gate insulating film 16. Thus, such a structure of the vertical MOS transistor 1 is constituted that the source region 13 and the drain region 15 are arranged to be separated from each other through the channel region 14 in the vertical direction perpendicular to the surface 9 of the Si epitaxial layer 8.

The contact trench 4 passing through the source region 13 from the surface 9 of the Si epitaxial layer 8 so that the deepest portion reaches the channel region 14 is formed in each unit cell 2. An opening width W of the contact trench 4 is constant in the depth direction thereof, and 0.2 μm to 0.5 μm, for example. The source region 13 is exposed on side surfaces 18 of the contact trench 4, while the channel region 14 is exposed on a bottom surface 19 of the contact trench 4.

A channel contact region 20 of a p⁺ type (having a concentration of 1×10¹⁹ to 1×10²⁰ cm⁻³, for example) is formed in the channel region 14 exposed on the bottom surface 19 of the contact trench 4. The channel contact region 20 is linearly formed on the whole bottom surface 19 of the contact trench 4 along the longitudinal direction of the contact trench 4.

An interlayer dielectric film 21 is formed on the Si epitaxial layer 8. A contact hole 22 exposing the contact trench 4 is formed in the interlayer dielectric film 21.

A source electrode (not shown) is formed on the interlayer dielectric film 21, to be collectively in contact with all unit cells 2 (the source regions 13 and the channel contact regions 20) through the respective contact trenches 4. In other words, the source electrode serves as a wire common to all unit cells 2. A drain electrode is formed on a back surface 7 of the Si substrate 5, to cover the whole area thereof. The drain electrode serves as an electrode common to all unit cells 2.

According to this embodiment, a portion of the channel region 14 located immediately under the contact trench 4 projects (bulges) in the form of a crest in sectional view in a direction separating from the channel contact region 20.

More specifically, the channel region 14 projects in the form of a parabola drawn to have both ends in the vicinity of a channel portion 23 of the channel region 14 where a channel is formed in operation of the MOS transistor 1 so that one peak (a top portion 25) reaches a position under a central portion in the width direction of the bottom surface 19 of the contact trench 4 from these ends. Thus, the channel region 14 has a projection 24 projecting from an end portion of the channel portion 23 closer to the back surface 10 of the Si epitaxial layer 8 toward the back surface 10 as a portion partitioned by the parabola.

The top portion 25 (the peak of the parabola) of the projection 24 is positioned on a side of the bottom surface 12 of the gate trench 12 closer to the back surface 10 of the Si epitaxial layer 8 (i.e. deeper than the bottom surface 12 of the gate trench 3) in a range not coming into contact with the Si substrate 5, and linearly formed along the contact trench 4. Preferably, the conductivity type of the projection 24 is the same p⁻ type (having a concentration of 1×10¹⁷ to 5×10¹⁷ cm⁻³, for example) as the channel region 14, and the impurity concentration therein is not more than 1/100 of that in the channel contact region 20 of the p⁺ type (having the concentration of 1×10¹⁹ to 1×10²⁰ cm⁻³, for example).

In the channel region 14, the thickness T₂ of the channel portion 23 is 0.5 μm to 0.9 μm, for example, and more specifically, 0.8 μm. The thickness T₃ up to the top portion 25 of the projection 24 is 1.0 μm to 1.6 μm, for example, and more specifically, 1.4 μm.

FIGS. 3A to 3J partially illustrate manufacturing steps for the trench gate MOS transistor 1 shown in FIG. 2 along cutting plane lines on the same position as that in FIG. 2.

In order to manufacture the MOS transistor 1, an Si crystal is grown on the surface 6 of the Si substrate 5 while doping an n-type impurity by epitaxy such as CVD (Chemical Vapor Deposition), LPE (Liquid Phase Epitaxy) or MBE (Molecular Beam Epitaxy), as shown in FIG. 3A. Thus, the n⁻-type Si epitaxial layer 8 (the drain region 15) is formed on the Si substrate 5. Then, a p-type impurity and an n-type impurity are successively implanted into the surface 9 of the Si epitaxial layer 8. After the implantation, the implanted p- and n-type impurities are activated by annealing (at 900° C. to 1000° C. for 10 minutes to 30 minutes, for example), thereby simultaneously forming the channel region 14 and the source region 13. Then, an SiO₂ film 26 is formed on the surface 9 of the Si epitaxial layer 8 by CVD, for example, and an SiN film 27 is formed on the SiO₂ film 26, thereby forming a two-layer hard mask 28 consisting of the SiO₂ film 26 and the SiN film 27. The thickness of the SiO₂ film 26 is set to 50 Å to 100 Å, for example, and the thickness of the SiN film 27 is set to 1000 Å to 1500 Å, for example.

Then, the Si epitaxial layer 8 is etched through the hard mask 28, as shown in FIG. 3B. Thus, the Si epitaxial layer 8 is dry-etched from the surface 9, to form the gate trenches 3. At the same time, the plurality of unit cells 2 are formed in the Si epitaxial layer 8.

Then, the gate insulating films 16 are formed on the inner surfaces (the side surfaces 11 and the bottom surfaces 12) of the gate trenches 3 by thermal oxidation (at 850° C. to 950° C. for 10 minutes to 30 minutes, for example), for example, as shown in FIG. 3C.

Then, doped polysilicon (an electrode material) is deposited from above the Si epitaxial layer 8 by CVD, for example, as shown in FIG. 3D. The deposition of the polysilicon is continued until at least the surface 9 of the Si epitaxial layer 8 is concealed. Thereafter the deposited polysilicon is etched back until the etched-back surface is flush with the surface 9 of the Si epitaxial layer 8. Thus, the gate electrodes 17 consisting of the polysilicon remaining in the gate trenches 3 are formed.

Then, the interlayer dielectric film 21 is formed by depositing SiO₂ (an insulating material) from above the Si epitaxial layer 8 by CVD, for example, as shown in FIG. 3E.

Then, each contact hole 22 is formed in the interlayer dielectric film 21 by dry etching, for example, as shown in FIG. 3F. After the formation of the contact hole 22, the exposed Si epitaxial layer 8 is etched through the interlayer dielectric film 21 employed as a mask. Thus, the Si epitaxial layer 8 is dry-etched from the surface 9, and each contact trench 4 is formed in a self-aligned manner with respect to the interlayer dielectric film 21.

Then, impurity ions (B₁₁ ions) are introduced in a direction perpendicular to the bottom surface 12 of the contact trench 4 thereby implanting the impurity ions by one stage into a depth position on a side of an interface 29 between the channel region 14 and the drain region 15 closer to the surface 9 of the epitaxial layer 8 (a portion of the channel region 14 in the vicinity of the interface 29), as shown in FIG. 3G. The implantation energy for the impurity ions is 100 keV to 140 keV, for example, and preferably about 140 keV. The dosage of the impurity ions is 4×10¹² cm⁻² to 1×10¹³ cm⁻², for example, and preferably 6×10¹² cm⁻² to 8×10¹² cm⁻².

After the implantation, the implanted p-type impurity ions are diffused and activated by annealing (at 900° C. to 950° C. for 0.5 minutes to 1 minute, for example) thereby forming the projection 24 of the channel region 14, as shown in FIG. 3H.

Then, impurity ions (BF₂ ions) are introduced in the direction perpendicular to the bottom surface 12 of the contact trench 4 at implantation energy of about 40 keV with a dosage of about 1×10¹⁵ cm⁻² thereby implanting the impurity ions by one stage into a depth position of the channel region 14 in the vicinity of the bottom surface 12, as shown in FIG. 31.

After the implantation, the implanted p-type impurity ions are diffused and activated by annealing (at 900° C. to 950° C. for 0.5 minutes to 1 minute, for example) thereby forming the channel contact region 20, as shown in FIG. 3J.

Thereafter the MOS transistor 1 shown in FIG. 2 is obtained by forming the source electrode (not shown), the drain electrode (not shown) and the like.

According to this embodiment, as hereinabove described, the channel region 14 partially projects as the projection 24 in the form of the parabola drawn to have both ends in the vicinity of the channel portion 23 of the channel region 14 so that one peak reaches the position under the central portion in the width direction of the bottom surface 19 of the contact trench 4 from these ends. Thus, the area of a p-n junction interface can be increased without influencing channel characteristics of the MOS transistor 1 as compared with such a conventional structure that the depth from the surface 9 of the Si epitaxial layer 8 to the interface (the p-n junction interface) between the channel region 14 and the drain region 15 is constant. In other words, only the portion of the channel region 14 located immediately under the contact trench 4 is projected without changing the length (the channel length) of the channel portion 23, whereby the channel characteristics are hardly influenced. Therefore, the area of a depletion layer spreading from the p-n junction is also increased, whereby the depletion layer receives voltage with a large area. Consequently, the voltage received per unit area of the depletion layer can be reduced.

Also in a case where the quantity L (in this embodiment, 0.2 μm to 0.1 μm, for example) of projection of the gate trench 3 toward the side of the interface between the channel portion 23 and the drain region 15 closer to the back surface 10 of the Si epitaxial layer 8 is small (the gate trench 3 is shallow) and withstand voltage cannot be ensured only with a depletion layer spreading from a small-area interface between the gate insulating film 16 and the drain region 15, therefore, the large-area depletion layer is present in the vicinity of the projection 24 of the channel region 14, whereby the withstand voltage of the overall MOS transistor 1 can be improved.

Therefore, gate-to-drain capacitance can be reduced by shallowing the gate trench 3 thereby reducing opposed areas of the gate electrode 17 and the drain region 15 while sufficiently holding source-to-drain withstand voltage.

Further, the projection 24 of the channel region 14 projects in the direction separating from the channel contact region 20, whereby the depletion layer spreading from the interface between the projection 24 and the drain region 15 can be prevented from coming into contact with the channel contact region 20. Therefore, reduction of the withstand voltage resulting from contact between the depletion layer and the channel contact region 20 can be avoided.

The projection 24 can be easily formed by introducing the impurity ions into the bottom surface 12 of the contact trench 4 lower by one stage than the surface 9 of the Si epitaxial layer 8 through the conventional ion implantation. Further, the projection 24 can be formed by introducing the impurity ions perpendicularly into the bottom surface 12 of the contact trench 4, whereby no precise angle adjustment is required in the implantation of the impurity ions while the implantation angle may not be switched.

The ion implantation system and the ion implantation depth for forming the projection 24 can be varied with the shape and the depth of the gate trench 3 and the shapes and the sizes of the impurity regions such as the source region 13 and the channel region 14.

For example, the impurity can be implanted by one stage into a depth position on the side of the interface 29 between the channel region 14 and the drain region 15 closer to the back surface 10 of the Si epitaxial layer 8 (a portion of the drain region 15 in the vicinity of the interface 29), as shown in FIG. 4(a).

Further, impurity ions can also be multistage-implanted over a plurality of stages by varying implantation energy in the range of 80 keV to 180 keV so that regions defined by implanted portions extend over the sides of the interface 29 closer to the surface 9 and the back surface 10 of the Si epitaxial layer 8 so that some of implantation depths of the impurity ions (B₁₁ ions) are on the side closer to the surface 9 of the epitaxial layer 8 and the rests are on the side closer to the back surface 10, as shown in FIG. 4B.

In a case of employing the multistage implantation, impurity ions may be implanted so that implantation depths of all impurity ions are on the side of the interface 29 closer to the back surface 10 of the Si epitaxial layer 8 as shown in FIG. 4C, or impurity ions may be implanted so that implantation depths of all impurity ions are on the side of the interface 29 closer to the surface 9 of the Si epitaxial layer 8 as shown in FIG. 4D.

Thus, a projection 24 of any shape can be formed by selecting the ion implantation system such as the single- or multistage system and the ion implantation depths. Therefore, the projection 24 of a proper shape can be formed in response to the shape and the depth of the gate trench 3 and the shapes and the sizes of the impurity regions such as the source region 13 and the channel region 14.

Drain-to-source breakdown voltage can be improved by setting the dosage of the impurity (B₁₁ ions) in the range of 4×10¹² cm ⁻² to 1×10¹³ cm⁻². More specifically, it was possible to set breakdown voltage to not less than 36 V when the dosage of B₁₁ ions was in the range of 4×10¹² cm⁻² to 1×10¹³ cm⁻², as shown in FIG. 5 (implantation energy=140 keV).

The projection 24 may not necessarily be partitioned by one parabola in sectional view, but may alternatively be partitioned by two parabolas, for example.

More specifically, a projection 31 of a channel region 30 preferably projects in the form of two parabolas drawn to have both ends in the vicinity of a channel portion 23 so that peaks (top portions 32) reach positions under first and second end portions in the width direction of a bottom surface 19 of a contact trench 4 respectively from these ends, as shown in FIG. 6. In this case, the respective top portions 32 of the projection 31 parallelly align with each other along the contact trench 4. The top portions 32 are preferably line-symmetrical with respect to a symmetry axis s formed by a perpendicular passing through a central portion in the width direction of the bottom surface 19 of the contact trench 4, and an opposite top portion 33 located on the symmetry axis s is preferably positioned on a side of the bottom surface 12 of the gate trench 3 closer to a back surface 10 of an Si epitaxial layer 8 (i.e., on a position deeper than the bottom surface 12 of the gate trench 3).

The projection 31 shown in FIG. 6 can be formed by carrying out a first step of implanting impurity ions into the first end portion in the width direction of the contact trench 4 at an implantation angle θ₁ inclining by 7° to 14° with respect to the bottom surface 12 of the contact trench 4 and a second step of implanting impurity ions into the second end portion in the width direction of the contact trench 4 at an implantation angle θ₂ inclining by 7° to 14° with respect to the bottom surface 12 of the contact trench 4 to intersect with the direction of introduction of the impurity ions in the first step, in place of the step shown in FIG. 3G, for example.

While the implantation angle for the impurity ions must be switched (θ₁→θ₂) according to the method when shifting from the first step to the second step, the projection 31 has the plurality of top portions 32 (peaks) and hence the area of an interface between the projection 31 and a drain region 15 can be further increased. Consequently, voltage received per unit area of a depletion layer can be further reduced.

While the embodiment of the present invention has been described, the present invention may be embodied in other ways.

For example, the unit cells 2 may not necessarily be arranged in a striped manner, but may be arranged in the form of a matrix as shown in FIG. 8, or may be arranged in a zigzag manner as shown in FIG. 9.

Further, each unit cell 2 is not restricted to the striped shape (FIG. 1) or a square pole shape (FIG. 8 or 9), but may be in the form of another polygon such as a triangular, pentagonal or hexagonal prism, for example.

In the MOS transistor 1, the conductivity types of the semiconductor portions may be reversed. For example, the p-type and n-type portions of the MOS transistor 1 may alternatively be formed as n-type and p-type portions respectively.

The Si epitaxial layer 8 may be replaced with an SiC epitaxial layer, for example.

The projection of the channel region may not necessarily be located immediately under the contact trench 4 as the projection 24 or 31, but may be formed on any other position in the range not influencing the channel characteristics of the MOS transistor 1.

Further, various modifications may be made to the design in the range of the scope of Claims for Patent.

<Invention Related to Reference Example> (Background Technique of Reference Example)

For example, a semiconductor device according to Patent Document 2 (Japanese Unexamined Patent Publication No. 2010-021176) is known as an example of a MOSFET.

The semiconductor device can be formed as a p-channel power MOSFET (Metal-Oxide-Semiconductor Field-Effect transistor) including a trench gate. The semiconductor device includes a semiconductor substrate constituted of a p⁺-type silicon substrate, a p-type semiconductor layer formed thereon and an n-type channel layer formed thereon.

The semiconductor device further includes an n⁺-type body region formed on a surface of the semiconductor substrate on the channel layer and a p⁺-type source region surrounding all sides of the body region in plan view. Further, the semiconductor device includes a gate trench passing through the channel layer to reach the p-type semiconductor layer, a gate insulating film formed on a side surface of the gate trench, a thick oxide film, having a larger thickness than the gate oxide film, formed on a bottom surface of the gate trench, and a gate electrode formed in the gate trench on the gate oxide film and the thick oxide film to fill up the gate trench.

The semiconductor device further includes a source electrode formed on the semiconductor substrate, an interlayer dielectric film formed on the gate electrode to insulate the gate electrode and the source electrode from each other, and a drain electrode provided on a back surface of the semiconductor substrate opposite to the surface provided with the source electrode in contact with the silicon substrate.

(Problem to be Solved by Reference Example)

According to Patent Document 2, the source region is formed by selectively implanting impurity ions into the semiconductor substrate and heat-treating the same after forming the gate electrode by removing polysilicon exposed from the gate trench by etchback.

In this method, however, there is an apprehension that the source region formed by ion implantation has a depth exceeding a designed value and the channel layer located immediately under the same is partially altered to the source region. Due to the alteration, the thickness of the channel layer is disadvantageously reduced below a designed value, to reduce the channel length.

The upper surface (the etched-back surface) of the gate electrode is frequently indented with respect to the surface of the semiconductor surface, due to low working accuracy of the etchback. Therefore, the impurity ions implanted into the surface of the semiconductor substrate are partially implanted into the semiconductor substrate also from the side surface of the gate trench exposed around the etched-back surface of the gate electrode.

An object of Reference Example is to provide a semiconductor device allowing precise control of a channel length and a method of manufacturing the same.

Another object of Reference Example is to provide a semiconductor device capable of compatibly attaining high withstand voltage and low on-resistance and a method of manufacturing the same.

(Embodiment of Reference Example)

An embodiment of Reference Example is now described in detail with reference to the attached drawings.

FIG. 10 is a schematic plan view of a MOS transistor according to the embodiment of Reference Example. FIG. 11 is a bird's-eye sectional view of the MOS transistor taken along a cutting plane line XI-XI in FIG. 10.

Referring to FIG. 10, a MOS transistor 41 as a semiconductor device includes a plurality of striped unit cells 42 arrayed in parallel with one another. The MOS transistor 41 is partitioned into the unit cells 42 by striped gate trenches 43, and the interval between each adjacent pair of gate trenches 43 (a pitch P of the gate trenches 43) is 0.9 μm to 1.5 μm, for example. Each unit cell 42 is provided with an elongated contact trench 44 (rectangular in plan view) extending from a first longitudinal end toward a second longitudinal end thereof.

Referring to FIG. 11, the MOS transistor 41 includes a substrate 45 as a semiconductor layer made of Si of an n⁺ type (having a concentration of 1×10¹⁹ to 5×10¹⁹ cm⁻³, for example). The substrate 45 functions as a drain of the MOS transistor 41, and contains phosphorus (P), arsenic (As) or the like as an n-type impurity. This also applies to the following description.

An epitaxial layer 48 made of Si of an n⁺ type (having a concentration of 1×10¹⁶ to 1×10¹⁵ cm⁻³, for example) lower in concentration than the substrate 45 is stacked on a surface 46 (the upper surface) of the substrate 45. The thickness of the epitaxial layer 48 as the semiconductor layer is 3 μm to 50 μm, for example, and the total thickness of the semiconductor layers including the substrate 45 and the epitaxial layer 48 is 70 μm to 300 μm, for example.

The gate trenches 43, having side surfaces 51 and bottom surfaces 52, dug down from the surface 49 toward the substrate 45 are formed in the epitaxial layer 48 in a striped manner. Thus, the plurality of striped unit cells 42 partitioned by the side surfaces 51 of the striped gate trenches 43 are formed in the epitaxial layer 48.

The gate trenches 43 are deep trenches having a depth D₁, measured from the surface 49 of the epitaxial layer 48, of 30 μm to 50 μm (more specifically, 40 μm), for example, and pass through the epitaxial layer 48, so that deepest portions thereof are positioned in an intermediate portion in the thickness direction of the substrate 45.

A gate insulating film 53 is formed on the inner surfaces of the gate trenches 43 and peripheral edge portions of the gate trenches 43 on the surface 49 of the epitaxial layer 48, to integrally cover the same. The thickness of the gate insulating film 53 is 0.025 μm to 0.15 μm, for example.

Gate electrodes 54 are formed to be opposed to the epitaxial layer 48 through the gate insulating film 53. The gate electrodes 54 are made of polysilicon doped with an impurity in a high concentration, for example.

The gate electrodes 54 integrally include trench portions 55 charged into the gate trenches 43 and planar portions 56 drawn from end portions closer to opening ends of the trench portions 55 on both sides of the end portions in the width direction (the lateral direction) of the gate trenches 43 along the surface 49 of the epitaxial layer 48, and are formed in a T-shaped manner in sectional view.

In the vicinity (on a surface portion) of the surface 49 of the epitaxial layer 48, channel layers 57 of a p⁻ type (having a concentration of 1×10¹⁷ to 5×10¹⁷ cm⁻³, for example) are formed around the gate trenches 43. The channel layers 57 contain boron (B), aluminum (Al) or the like, for example, as a p-type impurity. This also applies to the following description. In the epitaxial layer 48, a portion on a side of the channel layers 57 closer to a back surface 50 of the epitaxial layer 48 forms a drain layer 58.

On corner portions (trench corner portions 59) of the gate trenches 43 formed by the side surfaces 51 of the gate trenches 43 and the surface 49 of the epitaxial layer 48 intersecting with one another, the channel layers 57 are formed to hold the gate trenches 43 from both sides in the width direction thereof, and exposed on both of the surface 49 of the epitaxial layer 48 and the side surfaces 51 of the gate trenches 43. Thus, side surface portions 60 opposed to the trench portions 55 of the gate electrodes 54 and surface portions 61 opposed to the planar portions 56 of the gate electrodes 54 are formed on the channel layers 57 in the form of L shapes perpendicularly intersecting with one another on the trench corner portions 59. The depth D₂ of the channel layers 57 (the depth of the side surface portions 60) is smaller than that of the gate trenches 43, and 0.5 μm to 3.0 μm, for example.

On surface portions of the epitaxial layer 48 in the channel layers 57, source layers 62 are formed to be exposed on the surface 49. The source layers 62 are source wells so formed that the peripheries and lower portions thereof are entirely surrounded by the channel layers 57, which are interposed between the source layers 62 and the drain layer 58.

The source layers 62 integrally have overlap portions 63 entering portions located under end portions of the planar portions 56 of the gate electrodes 54 by prescribed quantities to overlap with part of the planar portions 56 and to be adjacent to the surface portions 61 of the channel layers 57 on a side opposite to the gate trenches 43 and contact portions 64 exposed on side surfaces 65 (described later) of the contact trench 44.

Depths of the source layers 62 vary with positions along the surface 49 of the epitaxial layer 48, and the overlap portions 63 are shallower than the contact portions 64, for example. More specifically, the depth D₃ of the overlap portions 63 is 0.2 μm to 1.0 μm, for example, while the depth D₄ of the contact portions 64 is 0.3 μm to 1.1 μm, for example. The depths of the source layers 62 are not more than three times the thickness of the gate insulating film 53, from whichever positions along the surface 49 of the epitaxial layer 48 the same are measured.

Each unit cell 42 is provided with the contact trench 44 passing through the corresponding source layer 62 from the surface 49 of the epitaxial layer 48 so that the deepest portion thereof reaches the corresponding channel layer 57. An opening width W of the contact trench 44 is constant in the depth direction thereof, and 0.2 μm to 0.5 μm, for example. The contact portions 64 of the source layer 62 are exposed on the side surfaces 65 of the contact trench 44, while the channel layer 57 is exposed on a bottom surface 66 of the contact trench 44.

A channel contact region 67 of a p⁺ type (having a concentration of 1×10¹⁹ to 1×10²⁰ cm⁻³, for example) is formed on the channel layer 57 exposed on the bottom surface 66 of the contact trench 44. The channel contact region 67 is linearly formed on the whole bottom surface 66 of the contact trench 44 along the longitudinal direction thereof.

An interlayer dielectric film 68 is formed on the epitaxial layer 48 to cover the gate electrodes 54 (the planar portions 56). Contact holes 69 exposing the contact trenches 44 are formed in the interlayer dielectric film 68.

A source electrode (not shown) is formed on the interlayer dielectric film 68, to be collectively in contact with all unit cells 42 (the source layers 62 and the channel contact regions 67) through the contact trenches 44. In other words, the source electrode serves as a wire common to all unit cells 42. A drain electrode is formed on a back surface 47 of the substrate 45, to cover the whole area thereof. The drain electrode serves as an electrode common to all unit cells 42.

FIGS. 12A to 12H partially illustrate manufacturing steps for the MOS transistor 41 shown in FIG. 11 in step order along cutting plane lines on the same position as FIG. 11.

In order to manufacture the MOS transistor 41, an Si crystal is grown on the surface 46 of the substrate 45 by epitaxy such as CVD (Chemical Vapor Deposition), LPE (Liquid Phase Epitaxy) or MBE (Molecular Beam Epitaxy) while doping n-type impurity ions, as shown in FIG. 12A. Thus, the n⁻-type epitaxial layer 48 (the drain layer 58) is formed on the substrate 45. Then, p-type impurity ions (B ions) are implanted into the surface 49 of the epitaxial layer 48. After the implantation, the implanted p-type impurity ions are activated by annealing (at 900° C. to 1000° C. for 10 minutes to 30 minutes, for example), thereby forming the channel layer 57.

Then, an SiO₂ film 70 is formed on the surface 49 of the epitaxial layer 48 and an SiN film 71 is formed on the SiO₂ film 70 by CVD, for example, thereby forming a hard mask 72 consisting of a two-layer film including the SiO₂ film 70 and the SiN film 71, as shown in FIG. 12B. The thickness of the SiO2 film 70 is set to 50 Å to 100 Å, for example, and the thickness of the SiN film 71 is set to 1000 Å to 1500 Å, for example. Then, the epitaxial layer 48 and the substrate 45 are partially etched through the hard mask 72 to pass through the channel layer 57 and the drain layer 58. Thus, the epitaxial layer 48 is dry-etched from the surface 48, to form the gate trenches 43. At the same time, the plurality of unit cells 42 are formed in the epitaxial layer 48.

Then, the gate insulating films 53 are formed on the inner surfaces (the side surfaces 51 and the bottom surface 52) of the gate trenches 43 by thermal oxidation (at 850° C. to 950° C. for 10 minutes to 30 minutes, for example), for example, as shown in FIG. 12C. At this time, the SiO₂ film 70 of the hard mask 72 is integrated with the gate insulating films 53 on the trench corner portions 59, to form the gate insulating film 53 on the surface 49 of the epitaxial layer 48. Thereafter the SiN film 61 of the hard mask 72 is removed.

Then, doped polysilicon is deposited from above the epitaxial layer 48 by CVD, for example, as shown in FIG. 12D. The deposition of the polysilicon is continued at least until the gate trenches 43 are filled up and the surface 49 of the epitaxial layer 48 is concealed. Thus, an electrode material layer 73 is formed. Then, a photoresist film 74 of a prescribed pattern is formed on the electrode material layer 73, which in turn is selectively etched by dry etching through the photoresist film 74 employed as a mask.

Thus, the gate electrodes 54 integrally including the trench portions 55 charged into the gate trenches 43 and the planar portions 56 drawn from end portions closer to the opening ends of the trench portions 55 on both sides of the end portions in the width direction (the lateral direction) of the gate trenches 43 along the surface 49 of the epitaxial layer 48 are formed, as shown in FIG. 12E.

Then, the gate electrodes 54 (the planar portions 56) are utilized as masks for implanting n-type impurity ions (As ions) into the surface 49 of the epitaxial layer 48 at an implantation angle θ₁ inclining by 3° to 14° with respect to the surface 49 of the epitaxial layer 48, as shown in FIG. 12E (a first step).

Then, the same n-type impurity ions are implanted into the surface 49 of the epitaxial layer 48 from a side of the gate trenches 43 opposite to the implantation position in the first step at an implantation angle θ₂ inclining by 3° to 14° with respect to the surface 49 of the epitaxial layer 48 to intersect with the direction of introduction of the n-type impurity ions in the first step. After the implantation, the implanted n-type impurity ions are activated by annealing (at 900° C. to 1000° C. for 10 minutes to 30 minutes, for example), thereby forming the source layers 62 in a self-aligned manner with respect to the planar portions 56.

While the overlap portions 63 entering the portions located under the planar portions 56 of the gate electrodes 54 are formed on the source layers 62 in the first and second steps, portions of the channel layers 57 provided with the overlap portions 63 are covered with the planar portions 56 in the ion implantation. Therefore, the overlap portions 63 are relatively shallowly formed (D₃<D₄), dissimilarly to the portions (the contact portions 64) into which the n-type impurity ions are directly implanted.

Then, the interlayer dielectric film 68 is formed by depositing SiO₂ (an insulating material) from above the epitaxial layer 48 by CVD, for example, as shown in FIG. 12F.

Then, each contact hole 69 is formed in the interlayer dielectric film 68 by dry etching, for example, as shown in FIG. 12G. After the formation of the contact hole 69, the interlayer dielectric film 68 is utilized as a mask to etch the exposed epitaxial layer 48. Thus, the epitaxial layer 48 is dry-etched from the surface 49, whereby each contact trench 44 is formed in a self-aligned manner with respect to the interlayer dielectric film 68.

Then, an impurity is implanted by one stage into a depth position of the channel layer 57 in the vicinity of the bottom surface 66 by introducing p-type impurity ions (BF₂ ions) in a direction perpendicular to the bottom surface 66 of the contact trench 44 at implantation energy of about 40 keV with a dosage of about 1×10¹⁵ cm⁻³, as shown in FIG. 12H. After the implantation, the implanted p-type impurity ions are diffused and activated by annealing (at 900° C. to 1000° C. for 0.5 minutes to 1 minute, for example), thereby forming the channel contact region 67.

Thereafter the MOS transistor 41 shown in FIG. 11 is obtained by forming the source electrode (not shown), the drain electrode (not shown) and the like.

In the MOS transistor 41, voltage exceeding threshold voltage is applied to the gate electrode 54 in a state where drain voltage is applied between the source layer 62 and the drain layer 58 (between a source and a drain), thereby generating an electric field from the gate electrode 54 (an ON-state). Thus, a channel perpendicularly feeding current along the side surface 51 of the gate trench 43 can be formed on the side surface portion 60 of the channel layer 57 while a channel laterally feeding current along the surface 49 of the epitaxial layer 48 can be formed on the surface portion 61 of the channel layer 57 at the same time, as shown in FIG. 13A. In other words, two-directional channels including a perpendicular channel and a lateral channel are formed in the channel layer 57, and the channels intersect with each other on the trench corner portion 59 to form an L-shaped channel as a whole.

The channel length of the L-shaped channel corresponds to the sum of the channel lengths of the perpendicular and lateral channels. The perpendicular channel length depends on the depth of the side surface portion 60 of the channel layer 57, while the lateral channel length depends on the width of the surface portion 61 of the channel layer 57.

When the channel layer 57 is formed with a designed depth in the step shown in FIG. 12A on the basis of implantation conditions for the p-type impurity ions in this embodiment, the side surface portion 60 of the channel layer 57 is covered with the planar portion 56 (a mask) of the gate electrode 54 in the subsequent step of implanting the n-type impurity ions for forming the source layer 62 shown in FIG. 12E. Therefore, the side surface portion 60 is not influenced by the n-type impurity ions. While the n-type impurity ions are obliquely implanted in this embodiment and hence the same are slightly implanted also into a portion located under the planar portion 56, the quantity of the n-type impurity ions is small and the implanted position remains in an end portion of the planar portion 56, whereby the side surface portion 60 of the channel layer 57 is not influenced by the n-type impurity ions. Therefore, the depth of the side surface portion 60 of the channel layer 57 can be precisely kept as designed in this embodiment, whereby the perpendicular channel length can be precisely controlled as designed.

While the width of the surface portion 61 of the channel layer 57 is influenced by the precision of the source layer 62 formed on the side thereof, the source layer 62 is formed in a self-aligned manner with respect to the planar portion 56 (the mask) of the gate electrode 54 formed by the etching excellent in working accuracy, as shown in FIG. 12E. Therefore, the source layer 62 can be prevented from excessively advancing toward the surface portion 61 of the channel layer 57 covered with the planar portion 56, whereby the width of the surface portion 61 of the channel layer 57 can be precisely controlled as designed by forming the planar portion 56 by etching the electrode material layer 73 as designed. Consequently, the lateral channel length can also be precisely controlled as designed, similarly to the perpendicular channel length.

According to the MOS transistor 41, part of the source layer 62 is formed as the overlap portion 63 to overlap with the planar portion 56 of the gate electrode 54, whereby the surface portion 61 of the channel layer 57 adjacent to the overlap portion 63 can be reliably opposed to the planar portion 56 of the gate electrode 54. Consequently, a highly reliable transistor operation can be performed.

Such an overlap portion 63 can be easily formed by positively implanting n-type impurity ions into the portion located under the planar portion 56 through the oblique implantation, as shown in FIG. 12E.

According to the MOS transistor 41, further, the gate trench 43 is a deep trench reaching the substrate 45 from the surface 49 of the epitaxial layer 48 through the channel layer 57 and the drain layer 58, whereby carriers (electrons) contained in the drain layer 58 can be induced to the vicinity of the side surface 51 of the gate trench 43 due to an electric field from the gate electrode 54 when the MOS transistor 41 is turned on. The induced carriers are stored to be uniformly distributed in the depth direction of the gate trench 43 along the side surface 51, to form a stratified carrier storage layer 75 in the vicinity of the side surface 51 of the gate trench 43.

When the MOS transistor 41 is in an ON-state, the carrier storage layer 75 can be utilized as a current path. Therefore, on-resistance of the MOS transistor 41 can be reduced, regardless of the value of resistance specific to the epitaxial layer 48. Therefore, high withstand voltage can be attained by increasing the thickness of the epitaxial layer 48 while keeping low on-resistance.

While the embodiment of Reference Example has been described, Reference Example may be embodied in other ways.

For example, the unit cells 42 may not necessarily be arranged in a striped manner, but may be arranged in the form of a matrix as shown in FIG. 14, or may be arranged in a zigzag manner as shown in FIG. 15.

Further, each unit cell 42 is not restricted to the striped shape (FIG. 10) or a square pole shape (FIG. 14 or 15), but may in the form of another polygon such as a triangular, pentagonal or hexagonal prism, for example.

In the MOS transistor 41, the conductivity types of the semiconductor portions may be reversed. For example, the p-type and n-type portions of the MOS transistor 41 may alternatively be formed as n-type and p-type portions respectively.

The ion implantation for forming the source layer 62 is not restricted to the oblique implantation implanting the ions in a direction inclining with respect to the surface 49 of the epitaxial layer 48, but perpendicular implantation implanting ions in a direction perpendicular to the surface 49 of the epitaxial layer 48 may be employed, for example.

The epitaxial layer 48 may be replaced with an SiC epitaxial layer, for example.

(Characteristics to be Grasped from Disclosure of Embodiment of Reference Example)

For example, the following invention (1) to (14) can be grasped from the disclosure of the embodiment of Reference Example:

(1) A semiconductor device including:

a first conductivity type semiconductor layer provided with a gate trench,

a gate electrode, opposed to the semiconductor layer through a gate insulating film, integrally including a trench portion charged into the gate trench and a planar portion laterally drawn from an end portion closer to an opening end of the trench portion along a surface of the semiconductor layer,

a second conductivity type channel layer, formed on a surface portion of the semiconductor layer to be exposed on both of the surface of the semiconductor layer and a side surface of the gate trench with a depth smaller than the depth of the gate trench, including a surface portion opposed to the planar portion of the gate electrode and a side surface portion opposed to the trench portion of the gate electrode, and

a first conductivity type source layer formed on the channel layer to be exposed on the surface of the semiconductor layer and adjacent to the surface portion of the channel layer on a side opposite to the gate trench.

(2) The semiconductor device according to (1), wherein

the source layer has an overlap portion entering a portion located under the end portion of the planar portion by a prescribed quantity and overlapping with part of the planar portion.

(3) The semiconductor device according to (2), wherein

the overlap portion of the source layer is shallower than the remaining portion of the source layer.

(4) The semiconductor device according to any one of (1) to (3), wherein

the depth of the source layer is not more than three times the thickness of the gate insulating film.

(5) The semiconductor device according to any one of (1) to (4), wherein

the gate trench includes such a deep trench that a storage layer of first conductivity type carriers contained in the semiconductor layer is formed along a side surface thereof due to an electric field from the gate electrode when the semiconductor device is turned on.

(6) The semiconductor device according to (5), wherein

the semiconductor layer includes a first conductivity type substrate and an epitaxial layer, formed on the substrate, having a lower impurity concentration than the substrate, and

the deep trench includes a trench reaching the substrate through the epitaxial layer.

(7) The semiconductor device according to any one of (1) to (6), wherein

the thickness of the semiconductor layer is 70 μm to 300 μm.

(8) The semiconductor device according to any one of (1) to (7), wherein

the depth of the gate trench is 30 μm to 50 μm.

(9) The semiconductor device according to any one of (1) to (8), wherein

the gate trench is formed to partition unit cells arrayed in a striped manner.

(10) The semiconductor device according to any one of (1) to (8), wherein

the gate trench is formed to partition unit cells arrayed in the form of a matrix.

(11) The semiconductor device according to any one of (1) to (8), wherein

the gate trench is formed to partition unit cells arrayed in a zigzag manner.

(12) A method of manufacturing a semiconductor device, including the steps of:

forming a channel layer to be exposed on a surface of a first conductivity type semiconductor layer by implanting second conductivity type ions into the semiconductor layer,

forming a gate trench deeper than the channel layer by etching the semiconductor layer from the surface to pass through the channel layer,

forming a gate insulating film on an inner surface of the gate trench and the surface of the semiconductor layer,

depositing an electrode material on the gate insulating film until the gate trench is filled up and the surface of the semiconductor layer is covered,

forming a gate electrode integrally including a trench portion charged into the gate trench and a planar portion laterally drawn from an end portion closer to an opening end of the trench portion along the surface of the semiconductor layer by patterning a portion of the electrode material other than the gate trench by etching, and

forming a source layer in a self-aligned manner with respect to the planar portion by implanting first conductivity type ions into the channel layer through the surface of the semiconductor layer in a state where a portion of the channel layer located under the planar portion is covered with the planar portion.

(13) The method of manufacturing a semiconductor device according to (12), wherein

the step of forming the source layer includes a step of obliquely implanting the first conductivity type ions at an implantation angle inclining with respect to the surface of the semiconductor layer so that part of the source layer enters a portion under an end portion of the planar portion by a prescribed quantity to form an overlap portion overlapping with part of the planar portion.

(14) The method of manufacturing a semiconductor device according to (13), wherein

the step of forming the gate trench includes a step of forming a striped trench so that unit cells are arrayed on the semiconductor layer in a striped manner, and

the step of obliquely implanting the first conductivity type ions includes a first step of obliquely implanting the first conductivity type ions into the striped trench from one side in the width direction and a second step of obliquely implanting the first conductivity type ions into the striped trench from a side opposite to an implantation position in the first step in a direction intersecting with a direction of introduction of the first conductivity type ions in the first step.

(Effects of Aforementioned Characteristics to he Grasped)

The semiconductor device according to (1) can be manufactured by the method of manufacturing a semiconductor device according to (12), for example.

According to the invention of (1) and (12), two-directional channels including a channel formed on a side surface portion of the channel layer by an electric field from the gate electrode or for perpendicularly feeding current along the side surface of the gate trench and a channel formed on a surface portion of the channel layer for laterally feeding current along the surface of the semiconductor layer can be formed.

The perpendicular channel length depends on the depth of the side surface portion of the channel layer, while the lateral channel length depends on the width of the surface portion of the channel layer.

When the channel layer is formed with a depth as designed on the basis of implantation conditions for the second conductivity type ions in the invention of Reference Example, the side surface portion of the channel layer is covered with the planar portion (a mask) of the gate electrode in subsequent step of implanting the first conductivity type ions for forming the source layer, whereby the same is not influenced by the first conductivity type ions. Therefore, the depth of the side surface portion of the channel layer can be precisely kept as designed, whereby the perpendicular channel length can be precisely controlled as designed.

While the width of the surface portion of the channel layer is influenced by the precision of the source layer formed on the side thereof, the source layer is formed in a self-aligned manner with respect to the planar portion (the mask) of the gate electrode formed by the etching excellent in working accuracy. The source layer can be prevented from excessively advancing toward the surface portion of the channel layer covered with the planar portion, whereby the width of the surface portion of the channel layer can be precisely controlled as designed by forming the planar portion by etching the electrode material as designed. Consequently, the lateral channel length can also be precisely controlled as designed, similarly to the perpendicular channel length.

Preferably in the semiconductor device according to Reference Example, the source layer has the overlap portion entering the portion located under the end portion of the planar portion by the prescribed quantity to overlap with part of the planar portion, as described in (2). In this case, the overlap portion of the source layer may be shallower than the remaining portion of the source layer, as described in (3).

According to the structure, the surface portion of the channel layer is reliably opposed to the planar portion of the gate electrode, whereby a highly reliable transistor operation can be performed.

In the semiconductor device according to Reference Example, the depth of the source layer may be not more than three times the thickness of the gate insulting film, as described in (4).

Preferably in the semiconductor device according to Reference Example, the gate trench includes such a deep trench that a storage layer of first conductivity type carriers contained in the semiconductor layer is formed along the side surface thereof due to an electric field from the gate electrode when the semiconductor device is turned on, as described in (5).

According to the structure, the carrier storage layer having low resistance is formed on the semiconductor layer, and can be utilized as a current path in an ON-state of the semiconductor device. Therefore, on-resistance of the semiconductor device can be reduced, regardless of the value of resistance specific to the semiconductor layer. Thus, high withstand voltage can be attained by increasing the thickness of the semiconductor layer while keeping low on-resistance.

More specifically, the deep trench preferably includes the trench reaching the substrate through the epitaxial layer when the semiconductor layer includes the first conductivity type substrate and the epitaxial layer, formed on the substrate, having a lower impurity concentration than the substrate, as described in (6).

Thus, the carrier storage layer can be formed on the whole section of the epitaxial layer, having a low impurity concentration and hindering reduction of the on-resistance, in the thickness direction, whereby a remarkable effect of reducing the on-resistance can be attained.

In the semiconductor device according to Reference Example, the thickness of the semiconductor layer may be 70 μm to 300 μm as described in (7), and the depth of the gate trench may be 30 μm am to 50 μm as described in (8).

The gate trench may be formed to partition any of the unit cells arrayed in a striped manner as described in (8), the unit cells arrayed in the form of a matrix as described in (10), and the unit cells arrayed in a zigzag manner as described in (11).

Preferably in the method of manufacturing a semiconductor device according to Reference Example, the step of forming the source layer includes the step of obliquely implanting the first conductivity type ions at the implantation angle inclining with respect to the surface of the semiconductor layer so that part of the source layer enters the portion under the end portion of the planar portion by the prescribed quantity to form the overlap portion overlapping with part of the planar portion, as described in (13).

According to the method, the first conductivity type ions can be positively implanted into the portion under the planar portion, whereby the overlap portion of the source layer can be easily formed.

Preferably, the step of obliquely implanting the first conductivity type ions includes the first step of obliquely implanting the first conductivity type ions into the striped trench from one side in the width direction and the second step of obliquely implanting the first conductivity type ions into the striped trench from the side opposite to the implantation position in the first step in the direction intersecting with the direction of introduction of the first conductivity type ions in the first step when the step of forming the gate trench includes the step of forming the striped trench so that the unit cells are arrayed on the semiconductor layer in a striped manner, as described in (14).

While the present invention has been described in detail by way of the embodiments thereof, it should be understood that these embodiments are merely illustrative of the technical principles of the present invention but not limitative of the invention. The spirit and scope of the present invention are to be limited only by the appended claims.

This application corresponds to Japanese Patent Application No. 2011-183041 filed with the Japan Patent Office on Aug. 24, 2011, Japanese Patent Application No. 2011-211443 filed with the Japan Patent Office on Sep. 27, 2011, and Japanese Patent Application No. 2012-132261 filed with the Japan Patent Office on Jun. 11, 2012, the disclosures of which are incorporated herein by reference. 

What is claimed is:
 1. A semiconductor device, comprising: a semiconductor layer having a first surface and a second surface; a trench formed on the first surface of the semiconductor layer; a first conductivity type first region formed to be exposed on a first surface side of the semiconductor layer, the first region forming part of a side surface of the trench; a second conductivity type second region formed on a second surface side of the first region, the second region forming part of the side surface of the trench; a first conductivity type third region formed on a second surface side of the second region, the third region forming a bottom surface of the trench; an insulating film formed on an inner surface of the trench; and a first electrode embedded inside the insulating film in the trench, wherein the second region integrally includes a first portion arranged closer to the first surface of the semiconductor layer than to the bottom surface of the trench, and a second portion projecting from the first portion toward the second surface of the semiconductor layer through the bottom surface of the trench, and the second portion of the second region defines a boundary surface with the third region which is inclined with the first surface of the semiconductor layer.
 2. The semiconductor device according to claim 1, further comprising a recess portion concaved from the first surface of the semiconductor layer toward the second surface thereof, the recess portion being disposed immediately above the second portion, wherein the second region defines a bottom surface of the recess portion.
 3. The semiconductor device according to claim 2, wherein the second region further includes a third portion on the bottom surface of the recess portion, the third portion having an impurity concentration higher than that of the first portion of the second region.
 4. The semiconductor device according to claim 2, wherein the second portion of the second region has a width wider than the largest width of the recess portion.
 5. The semiconductor device according to claim 1, wherein the third region is partly arranged between the side surface of the trench and the boundary surface of the second portion of the second region.
 6. The semiconductor device according to claim 1, wherein the second portion of the second region has a same impurity concentration as the first portion of the second region.
 7. The semiconductor device according to claim 6, wherein the impurity concentration of the first portion and the second portion is 1×10¹⁷ to 5×10¹⁷ cm⁻³.
 8. The semiconductor device according to claim 2, wherein the second region has a different impurity concentration from a bottom region of the recess portion.
 9. The semiconductor device according to claim 3, wherein the impurity concentration of the second portion is not more than 1/100 of that of the third portion.
 10. The semiconductor device according to claim 3, wherein a top portion of the second portion immediately under the third portion is formed along a position under a central portion in the width direction of the bottom surface of the recess portion.
 11. The semiconductor device according to claim 3, wherein a top portion of the second portion immediately under the third portion is formed along a position under an end portion in the width direction of the bottom surface of the recess portion.
 12. The semiconductor device according to claim 11, wherein the top portion of the second portion includes a plurality of top portions formed in parallel with one another along positions under both end portions in the width direction of the bottom surface of the recess portion.
 13. The semiconductor device according to claim 1, wherein the semiconductor layer consists of an Si semiconductor layer.
 14. The semiconductor device according to claim 10, wherein the second portion projects in the form of a parabola such that one top portion of the second portion reaches a position under the central portion in the width direction of the bottom surface of the recess portion.
 15. The semiconductor device according to claim 11, wherein the second portion projects in the form of two parabolas such that top portions of the second portion reach positions under a first and a second end portions in the width direction of the bottom surface of the recess portion respectively.
 16. The semiconductor device according to claim 15, wherein the respective top portions of the second portion parallelly align with each other along the recess portion.
 17. The semiconductor device according to claim 16, wherein the top portions are line-symmetrical with respect to a symmetry axis is formed by a perpendicular passing through the central portion in the width direction of the bottom surface of the recess portion.
 18. The semiconductor device according to claim 13, wherein the Si semiconductor layer includes an Si substrate and an Si epitaxial layer formed on the Si substrate, the Si epitaxial layer having a impurity concentration lower than that of the Si substrate, and a top portion of the second portion is not in contact with the Si substrate.
 19. The semiconductor device according to claim 1, wherein the thickness of the first portion is 0.5 μm to 0.9 μm and the thickness up to a top portion of the second portion is 1.0 μm to 1.6 μm.
 20. The semiconductor device according to claim 1, wherein quantity of projection of the trench from an interface between the first portion and the third region is 0.2 μm to 0.1 μm.
 21. The semiconductor device according to claim 2, wherein the recess portion has a stripe shape, and the second portion is formed in a stripe shape along the striped recess portion.
 22. The semiconductor device according to claim 2, wherein the recess portion is shallower than the trench.
 23. The semiconductor device according to claim 1, the insulating film includes silicon oxide film. 